1. Field of the Invention
This invention relates generally to programmable logic devices, and more particularly to programmable logic devices having buried state registers.
2. Description of the Related Art
As the technology for manufacturing integrated circuits progresses, it is becoming possible to put more and more discrete logic components on a single integrated circuit chip. For instance, there can be thousands of discrete logic components, such as, AND-gates, OR-gates, inverters and registers, on a single integrated circuit chip. However, due to limitations in packaging technology, the number of input and output ports to a given integrated circuit chip is limited. Thus, thousands of discrete logic components must be served typically by on the order of a few dozen input/output (I/O) ports. The small number of input/output ports available for a given integrated circuit thus severely restricts the flexibility in design of logic circuits implemented on integrated circuit chips.
Programmable logic devices such as the programmable array logic (PAL) device offer digital designers a flexible and cost effective implementation for complex logic circuits. PAL, an acronym for a Programmable Array Logic device, is a registered trademark of Advanced Micro Devices, Inc. A typical PAL device includes a fuse programmable array of AND gates, and a fixed array of OR gates. In some PAL devices, the outputs of the OR gates are coupled directly to an I/O pin, and in other PAL devices the outputs of the OR gates are input into clockable, D-type or S/R-type registers.
Flexibility in design is particularly important for devices such as programmable array logic devices. In a programmable array logic device, a user of the device configures the logic array according to a specific need using field programming techniques. Since the user is constrained in his design choices by the configuration of the input/output pins, the utility of the programmable logic array is limited.
A prior U.S. patent application owned by the assignee in common with the present application, entitled PROGRAMMABLE INPUT/OUTPUT CELL WITH FLEXIBLE CLOCKING AND FLEXIBLE FEEDBACK, Ser. No. 795,159, filing date of Nov. 5, 1985, addresses one way in which the configuration of input/output ports may be made more flexible. There, the user is able to select from a variety of input modes or a variety of output modes for a given input/output pin by setting a selector means using field programming techniques, such as blowing a fuse or not blowing the fuse, when the designer sets up the logic circuit on the chip in conjunction with user-determined "product terms" generated within the logic array. In the input mode the port may be configured as a dedicated, registered, or latched input; in the output mode as registered, combinatorial or latched output. A register/latch, in conjunction with a fuse-programmable input select multiplexer, can function as an input, output or buried register or as a transparent latch. A programmable clock select multiplexer selects between a clock/latch enable signal applied at an external pin or a product term generated internally. Clock polarity control is also provided. Asynchronous reset and preset of the register/latch is provided along with polarity control therefor. Dedicated and programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an external pin. The input/output circuit can be deployed in banks, each bank selectably receiving the same or a different clock. The register/latch can be preloaded via an internally-generated signal or from the external pins. Thus, for example, the designer is able to locate registered outputs and combinatorial outputs on the I/O pins as he desires for a selected logic array package.
Another way in which to increase the flexibility of the design for programmable array logic devices of the prior art provides selectable feedback in the output logic so that the designer may choose using field programming techniques to provide a feedback path directly from the I/O pin to the logic array, in effect, treating the I/O pin as an input pin, or to select a registered output from the logic array as feedback. This sort of feedback system is described in product literature for the Advanced Micro Devices 24-pin IMOX.TM. Programmable Array Logic Device designated the AmPAL22V10 (PAL is a registered trademark of Monolithic Memories, Inc.). An advanced information sheet concerning the AmPAL22V10 was released by Advanced Micro Devices, Inc., Sunnyvale, Calif. dated June, 1983. This advanced information can be referred to for further background to the present invention.
Both the input selector and the feedback selector of the prior art mentioned above involve a designed-in or field programmed selection of the type of feedback or the type of output for a particular I/O pin. Accordingly, the user was limited to one configuration of each I/O pin for the device. Since it is desirable to provide a flexible output logic circuit, there is a need for an output logic circuit which provides for increased flexibility and overcomes the limitations of the prior art.
PAL devices having clockable registers are ideal for use as state machines or, as they are sometimes called, sequencers. A state machine includes a number of registers which store the current state of the machine, input combinatorial logic, and output combinatorial logic. Typically, the outputs of the input combinatorial logic determine the next state to be stored within the state registers, and the current state stored in the state registers form a part of the input to the output combinatorial logic. Quite frequently, outputs of the output combinatorial logic are fed back as inputs to the input combinatorial logic.
Frequently, the contents of registers within the programmable array logic devices used solely as state machine counters need not be conducted to I/O pins, since their contents are used internally for counting purposes. However, the prior art has nevertheless allocated an I/O pin to each of such registers for such PAL sequencers.
Complex state machine designs push the limits of prior art PAL devices. For a variety of practical technical and economic reasons, it is desirable to keep the PAL device package as small as possible and to limit the number of pins associated with the package. PAL device designers found that one way to shrink package size is to provide several "buried" state registers which can be used to store the current state number, and separate output registers which can output data to an I/O pin. By not assigning a I/O pin to the buried state registers the number of pins required to implement the device is reduced.
Thus, it is often desirable to deploy a register within the logic circuit as a dedicated buried state register. Accordingly, there is need for an input/output circuit which can be flexibly configured in which a so-called "buried," or internal, state register can be flexibly utilized. This feature allows the system designer to build improved state machines or sequencers.
However, mere provision of such accessible registers is not sufficient because a circuit must be tested by the designer. This requires dynamically observing the contents of these internal state registers during debugging and circuit verification.
Thus, a problem with the above-mentioned prior-art PAL design having separate buried state registers and output registers is that it is difficult to observe the contents of the buried state registers. With such designs, the output of a buried state register must be clocked through the output combinatorial logic and an output register before appearing at an I/O pin. This process can take several cycles, and is thus both inconvenient and time consuming.
Another problem with the above mentioned prior art PAL design is that it is difficult to preload the buried and output registers for debugging purposes. Without a preloading capability, a sequence of inputs to the device would have to be devised to attain a desired state within the PAL, which again is an inconvenient and time consuming process.
Further, while the prior art provides dedicated feedback, for the determination of states, from the registers allocated an I/O pin, a designer would like to permit the state to be a function of the contents of all registers, including the internal state registers. Accordingly, it would be desirable to have dedicated feedback from all registers, so that the designer can flexibly construct a state machine with a variable number of internal states and a variable number of registers allocated an I/O pin.
A further desirable feature is the ability to preload registers from the logic array, rather than applying a Zener level preload voltage, which may not be available during testing stages.
Provision of an independent combinatorial signal from a programmable OR portion of the logic array, separate from the signal received therefrom and stored in a register, is desirable in that the register may be used as a buried register when the signal received independently from the array is conducted to the I/O pin serving this register. This capability also allows the designer a different combinatorial and a different sequential output to be fed back from the same device, by selecting the output appropriately.
Furthermore, it is often desirable to allow clocking of the register of individual logic circuits from the logic array as well as from the usual clock, with selection by the user. It may even be desirable to permit user-selection from a pair of clocks, particularly when the integrated circuit chips employing the output logic circuits are deployed in two banks, each with its own clock.